2013年2月24日 星期日

Increased flexibility and power savings render greater display efficiency from Embedded DisplayPort

 While mobile device display performance continues to increase, system chip processes geometries continue to shrink, resulting in a greater proportion of system power consumed by the display and its high-speed interface. 

The new Embedded Display Port (eDP) v1.4 standard offers several new features that maximize system power efficiency, further consolidate the display interface, and address a wide range of system profiles to satisfy the growing demand for power optimization in the embedded display system.

 

Embedded PC, in vehicle computer, Industrial PC

 

Advanced link power management
The ability to manage the display interface is improved in eDP v1.4 by greatly reducing the wake-up time from the low-power state, which is important to maximize the efficiency of the PSR selective update process. Previous versions of eDP required more than 100 microseconds to wake up and retrain the data link. With eDP v1.4, if the new PSR mode is supported, wake-up from standby is a maximum 0.5 microseconds, and wake time from the lower-power sleep state is 20 microseconds.
Video timing synchronization
In DisplayPort and earlier versions of eDP, display-to-GPU synchronization is performed over the DisplayPort main link, the high-speed data channel that carries video data using special control codes. In eDP v1.4, frame synchronization is also provided over the lower-speed auxiliary channel. This enables quick bursts of eDP main link operation to perform timely selective updates of the remote frame buffer.
Display stream compression
Display interfaces including DisplayPort and earlier versions of eDP send uncompressed pixel data across the display interface. Image compression is traditionally limited to media delivery to the system or for storage. In the interest of further power savings, eDP v1.4 introduces a display stream compression algorithm that reduces the data rate across the display interface. In contrast to typical video or image compression algorithms, the display stream compression algorithm is optimized for high data throughput, low latency, and low gate count and targets low-compression ratios in the 2x to 5x range, depending on the image type. By using a minimum 2x compression ratio configuration, for example, the display interconnect bandwidth can be cut in half, with typically no loss in image content. Display stream compression can also be used when updating a display’s PSR frame buffer, providing further power savings. It can also be used to support display resolutions beyond the uncompressed main link capability.
Regional backlight control
When eDP v1.2 was released in 2010, it introduced the capability to control LCD backlight modulation frequency and brightness through the auxiliary channel, thus eliminating the need for an extra backlight control interface. In eDP v1.4, regional backlight control provides the option to independently set different portions of the display backlight region. This allows the GPU to actively darken selective portions of the display based on display contents, increasing power savings. Up to 15 backlight regions can be controlled with a single auxiliary transaction.
Multitouch over auxiliary channel
Touch-sensitive displays are common in many smaller embedded display systems and will become more prevalent in PCs. The latest version of eDP adds the ability to transport multitouch data from the display to the host through the auxiliary channel. The multitouch data transport uses a framework that is compatible with the USB Human Interface Device specifications. By eliminating the dedicated USB interface commonly used for this purpose, both electrical connections and power are saved.
Reduced differential voltage swing
Prior to eDP v1.4, the standard utilized the same interface signal voltage amplitudes as DisplayPort. Today, eDP v1.4 reduces the main link’s minimum differential voltage amplitude levels from 400 mV to 200 mV, which is suitable for the short transmission distances in small embedded form factors. This reduces interface drive power by as much as 75 percent, as power is proportional to the square of amplitude. Additional flexibility is also added to the link training amplitude step sizes, helping increase suitability for different transmission media including chip-on-glass.
Increased link rate flexibility
Another addition in eDP v1.4 is greater flexibility in the main link data rate. Previous versions of eDP limited link rate selection to 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps per lane (main link data channel), which is the same as DisplayPort. The current version of eDP now includes seven standard rates, enabling further power efficiency.
With DisplayPort, increasing a 1080p 60 Hz display format from 24-bit color to 30-bit color would require changing a two-lane 2.7 Gbps configuration to either a four-lane 2.7 Gbps configuration or a two-lane 5.4 Gbps configuration. Ether case represents a 100 percent increase in interface bandwidth and power, with only a 25 percent increase in data content (additional dummy bits would be added to make up the difference). With eDP v1.4 in the same application, the rate could be bumped up from 2.7 Gbps to 3.24 Gbps, resulting in only a 20 percent link rate increase.
Customizable link rates are also supported, with a new set of registers defined for the display to declare this capability, as well as the custom link rate frequency. In addition to further power optimization, this increases application diversity as link rates can be adjusted based on particular system timing requirements. It also enables link rate adjustment to mitigate radio frequencyinterference with system wireless services.
System deployment with eDP v1.4
Offering increased flexibility and reduced system power, the latest release of eDP v1.4 will help propel eDP into new applications and establish it as a universal embedded display interface. Given the current cycle of eDP standard publication and adoption, it is expected that systems using some of the new features in eDP v1.4 will appear on the market in two to three years. Higher-resolution notebook PCs and tablets will likely be the first candidates to leverage this power-optimized interface.

 



 refer:

http://embedded-computing.com/articles/embedded-greater-display-efficiency/#at_pco=cfd-1.0

 

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